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While due to recession a fresher's dream of joining the world of work is getting delayed, but here there is something to rejoice for all electronics students who aspire to enter the world of VLSI and do marvel !! Mentor Graphics, world leader of EDA tools is conducting
a program Introduction to Verification of Electronic Design and Systems using System Verilog which is all sponsored by Mentor Graphics. The best part is 15 days long program is all free for students.
Program Description
- Introduction to Logic Design and Verification (Block level and System Level)
- Introduction to SystemVerilog Open Verification Methodology
- Concepts of Verification Management and Coverage using Questa Verification environment
Venue: Mentor Graphics (India) Pvt. Ltd., Building A, Plot # 5, Sector-127 Noida
Timings: 10 AM to 6 PM (Lunch Provided)
Date: October 19, 2009 – December 7, 2009
- B.Tech or B.E. degree graduates in Electronics, Computer Science and Electrical are eligible with a CGPA of 6.5 and above.
- The candidate should not have an offer of joining any company till December 2009
- Short-listedcandidates will be called for a written test in order to qualify forthe course.
- The test will be held at Mentor Graphics, Noida onSeptember 19, 2009. The selected candidate will have to make his/herown stay arrangements.
Note: Course fee: NIL
So, students what you waiting for Log on and sign up: http://www.mentor.com/india/ .
"Verification of Electronic Design and Systems using System Verilog” for students whohave graduated from Delhi NCR colleges and who have not yet found placement. The course will be for eight weeks beginning October 19 –December 7, 2009 from 10am to 6pm (Monday to Friday). The program willinclude extensive labs using Mentor Tools and will also include someprojects.
Some of the Key Modules of the program are:
Program Details:
Eligibility: